Improvements in microprocessor designs have led to microprocessors with a high operating frequency. Current microprocessor designs may exceed operating frequencies of 200 megahertz (MHz). However, the increase in operating frequency typically has not led to fully acceptable performance gains. One of the main components affecting performance gains is created by the microprocessor execution units idling during delays in external memory access. The delays in external memory access are caused by the conventional design characteristics of static random access memory (SRAM) cells, read only memory (ROM) cells, and dynamic random access memory (DRAM) cells.
To counteract the performance losses associated with external memory access, Rambus Inc., of Mountain View, Calif. developed a high speed multiplexed bus. FIG. 1 is a typical prior art system using the Rambus high speed bus. In particular, the system 1000 comprises a master device, or central processing unit (CPU) 10, coupled to slave devices DRAM 20, SRAM 30, and ROM 40. Each device is coupled in parallel to signal lines comprising DATA BUS, ADDR BUS, CLOCK, VREF, GND, and VDD. The DATA BUS and ADDR BUS signal lines comprise the data and address lines, respectively, used by CPU 10 to access data from the slave devices. The CLOCK, VREF, GND, and VDD signal lines comprise the clock, voltage reference, ground, and power signals, respectively, shared between the multiple devices. Data is transferred by bus drivers (not shown) of each device driving signals onto the bus. The signals are transmitted across the bus to a destination device.
To increase the speed of external memory accesses, the system 1000 supports large data block transfers between the input/output (I/O) pins of CPU 10 and a slave device. The system 1000 also includes design requirements that constrain the length of the transmission bus, the pitch between the bus lines, and the capacitive loading on the bus lines. Using these design requirements the system 1000 operates at a higher data transfer rate than conventional systems. Accordingly, by increasing the data transfer rate, the system 100 reduces the idle time in CPU 10.
The system 1000, however, does not provide enough bus bandwidth for developing technologies. New technologies require data transfer rates greater than 500 megabits per second (Mb/s) per pin. Alternatively, new technologies require operation speeds of at least several hundred MHz. Operating at high frequencies accentuates the impact of process-voltage-temperature (PVT) on signal timings and signal levels. The PVT variances result in numerous disadvantages that create high transmission errors, or data loss, when operating the system 100 at a frequency of 400 MHz, for example.
A factor to be considered in high-speed bus operations is the precise control and timing of the memory devices coupled to the bus. When the memory system is operated at low frequencies, communications between the memory controller and all of the memory devices on the bus are generally completed within the period of one clock cycle. However, one disadvantage associated with operating the typical prior art memory system at a high frequency such as 400 MHz is that the system bus propagation delay between the memory controller and some memory devices is longer than one clock cycle. This results in communications between the memory controller and some memory devices taking longer than the period of one clock cycle to complete.
One method for dealing with this timing problem is to have the memory controller track the propagation delay times associated with each memory device so as to effectively manage the communications between each device and the memory controller. This technique, however, heavily tasks the memory controller and memory assets, thereby increasing the system memory requirements and introducing additional sources of delay due to the additional processing requirements. A significant cost increase can result from the use of this technique.
Numerous timing parameters are specified in multiple configuration registers of the memory devices. Taken together, these timing parameters typically specify communications between the memory controller and any number of memory devices. A problem with these prior art systems, however, is that the register fields of the typical memory devices are preprogrammed with reset values that are supposed to guarantee functionality at the fastest specified clock rate of a particular device. However, optimal performance can only be achieved when some of the parameters are adjusted from their preset values. These adjustments are performed by the memory controller using register write requests; however, it has proven problematic for the prior art memory controller to determine values at which these delays are set or to know values at which these delays are to be set. Typically, the only way for a memory controller to determine the reset value or to establish the optimum value is to query some form of device manufacturer register of the memory controller or the memory device for the vendor and memory identification, thereby allowing the memory controller to index through a look-up table of known optimal values. Unfortunately, this method does not allow for adjustments to compensate for process variations. Moreover, this method does not allow for dynamic adjustments to register values. Furthermore, this method fails for any memory devices introduced after the memory control Basic Input/Output System was set.
Another disadvantage in operating typical prior art memory systems at high frequencies is that correct functionality is guaranteed only when devices having the correct speed device are placed on the channel. However, with the introduction of memory devices having a variety of speed grades, correct functionality is no longer guaranteed as there is no way for the prior art memory controller to detect that a slow part is placed on a fast channel. The device may work most of the time, but fail under extreme operating or environmental conditions. This is a problem that has plagued the computer industry since the first memory devices were binned according to access time. Thus, as the memory device configuration registers determine so much of the behavior of the memory device, the memory device initialization procedure is a vital element of the overall controller-memory interface.
Typical prior art memory systems take advantage of low power modes during processor lulls in order to reduce the overall system power consumption. These low power modes are modes in which memory components or devices may be placed in lower frequency modes during periods of inactivity or reduced activity. Another disadvantage of these prior art memory systems is that a substantial delay in processing times may be incurred in waiting for these components to return to the higher frequency mode.